There are issues with the amount of power that buses use when communicating data between an Ethernet physical layer (PHY) and an Ethernet media access control (MAC) layer. Various interface such as xAUI (XAUI, RXAUI, etc.) and xMII (GMII, RGMII, SGMII, etc.) buses interconnect an Ethernet PHY and an Ethernet MAC (typically in a CPU). The more SerDes lanes that are utilized, the more power is used. A SerDes lane is a Serializer/Desirializer which is a pair of functional blocks commonly used in communication to compensate for limited input/output.